Material composition and methods thereof

ABSTRACT

Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/434,811, filed Dec. 15, 2016, the entirety of which is incorporatedby reference herein.

BACKGROUND

The electronics industry has experienced an ever increasing demand forsmaller and faster electronic devices which are simultaneously able tosupport a greater number of increasingly complex and sophisticatedfunctions. Accordingly, there is a continuing trend in the semiconductorindustry to manufacture low-cost, high-performance, and low-powerintegrated circuits (ICs). Thus far these goals have been achieved inlarge part by scaling down semiconductor IC dimensions (e.g., minimumfeature size) and thereby improving production efficiency and loweringassociated costs. However, such scaling has also introduced increasedcomplexity to the semiconductor manufacturing process. Thus, therealization of continued advances in semiconductor ICs and devices callsfor similar advances in semiconductor manufacturing processes andtechnology.

Generally, the minimum feature size of a given semiconductor IC is afunction of the wavelength of a radiation source used in a lithographyprocess, as well as a resist composition and resist selectivity, amongother factors. As semiconductor lithography has progressed, thewavelength of the radiation source used has decreased, and the radiationsource itself may be relatively weak, such that photoresists have beendesigned to utilize radiation sources as efficiently as possible. As oneexample, chemically amplified photoresist (CAR) compositions have beenintroduced in an effort to increases a resist's sensitivity to anexposing light source. However, CAR systems have encountered limitationswhich are difficult to overcome, such as poor photon absorption in thinfilms, moderate etch selectivity, and limited gains in resolution.Moreover, the need for photoresists with high resolution, low line widthroughness (LWR), and high sensitivity has increased more rapidly thanthe capability provided by such CAR systems. As such, chemicallyamplified resists alone may not be able to satisfy the next generationlithography requirements demanded by the continued advances insemiconductor technology.

Thus, existing techniques have not proved entirely satisfactory in allrespects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A and 1B illustrate various aspects of a treatment material, inaccordance with some embodiments;

FIGS. 2A, 2B, 2C, 2D, 2E, and 2F illustrate examples of a treatmentmonomer (R_(t)), in accordance with some embodiments;

FIGS. 3A, 3B, and 3C illustrate examples of a grafting monomer (R_(g)),in accordance with some embodiments;

FIGS. 4A, 4B, and 4C illustrate examples of an etching resistancemonomer (R_(e)), in accordance with some embodiments;

FIG. 5 illustrates a flow chart of a method for using the treatmentmaterial as part of a post-treatment process, according to variousembodiments;

FIGS. 6A, 6B, and 6C provide cross-sectional views of a semiconductorstructure at various fabrication stages, constructed in accordance withthe method of FIG. 5;

FIG. 7 illustrates a flow chart of a method for using the treatmentmaterial as part of an in-situ treatment process, according to variousembodiments; and

FIGS. 8A, 8B, 8C, and 8D provide cross-sectional views of asemiconductor structure at various fabrication stages, constructed inaccordance with the method of FIG. 7.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The present disclosure is generally related to methods for semiconductordevice fabrication, and more particularly to material compositionsand/or complexes for treatment of a photoresist (resist) material inextreme ultraviolet (EUV) lithography, and methods of using the same. Insome cases, the embodiments shown and described herein may also be usedfor treatment of a resist material in deep UV (DUV) and electron beam(e-beam) lithography. Generally, lithographic patterning includescoating a substrate with a resist film, exposing the resist film to aradiation source (e.g., DUV, UV, or e-beam radiation source), anddeveloping the exposed resist in a developer (a chemical solution). Thedeveloper removes portions of the exposed resist, such as exposedportions of a positive-tone resist or unexposed portions of anegative-tone resist, thereby forming a patterned resist layer. Thepatterned resist layer may then be used as an etch mask in a subsequentetching processes, transferring the pattern of the patterned resistlayer to an underlying material layer. Alternatively, the resist patternis used as an ion implantation mask in a subsequent ion implantationprocess applied to the underlying material layer, such as an epitaxialsemiconductor layer.

Generally, the minimum feature size of a given semiconductor IC is afunction of the wavelength of the radiation source used in thelithography process, as well as the resist composition and resistselectivity, among other factors. As semiconductor lithography hasprogressed, the wavelength of the radiation source used has decreased,for example from 248 nm (e.g., for a KrF laser) to 193 nm (e.g., for anArF laser) for DUV lithography, and to 13.5 nm for EUV lithography.Radiation sources (light sources) used to produce these wavelengths oflight may be relatively weak, such that photoresists have been designedto utilize these light sources as efficiently as possible.Conventionally, this goal has been achieved in part by the use ofchemically amplified photoresists, where such chemical amplificationincreases a resist's sensitivity to the exposing light source.Currently, most semiconductor companies use chemically amplified resists(CAR) for high-volume manufacturing (HVM). Chemically amplified resistshave been used for 248 nm (e.g., for a KrF laser) and 193 nm (e.g., foran ArF laser) DUV lithography, as well as for 13.5 nm EUV lithography,but the need for photoresists with higher resolution, lower line widthroughness (LWR), and higher sensitivity has increased more rapidly thanthe capability provided by such resist systems. Adding to the challengeis the so-called “RLS tradeoff”, which is a name given to the verydifficult task of trying to simultaneously optimize resolution, LWR, andsensitivity. Thus, existing methods have been lacking, and may not beable to adequately satisfy next generation lithography requirements.

Embodiments of the present disclosure offer advantages over the existingart, though it is understood that other embodiments may offer differentadvantages, not all advantages are necessarily discussed herein, and noparticular advantage is required for all embodiments. Generally, and inaccordance with embodiments disclosed herein, a material composition andmethod for treating a resist material, and thereby improving at leastLWR and local critical dimension uniformity (LCDU), is provided. Invarious embodiments, the material composition may be used to treat theresist material as part of an in-situ treatment process or as part of apost-treatment process, as described in more detail below.

With reference to the example of FIGS. 1A and 1B, illustrated therein isa treatment material 100, in accordance with some embodiments. Invarious embodiments, the material composition for treating the resistmaterial (e.g., the treatment material 100) may include one or more of atreatment monomer (R_(t)), a grafting monomer (R_(g)), and an etchingresistance monomer (R_(e)). By way of example, the treatment monomer(R_(t)) may include an organic compound such as an aliphatic compound.In some embodiments, the treatment monomer (R_(t)) may include a C4-C20alkyl group, a cycloalkyl group, a C4-C20 saturated or unsaturatedhydrocarbon ring or a C5-C20 heterocyclic group which may include a 2-Dor 3-D structure. Additionally, in some embodiments, the glasstransition temperature (Tg) of the treatment monomer (R_(t)) may bebelow about 80 degrees Celsius. In some cases, the glass transitiontemperature (Tg) of the treatment monomer (R_(t)) may be below about 50degrees Celsius. Additional examples of the treatment monomer (R_(t))are provided in FIGS. 2A-2F. For example, the treatment monomer (R_(t))may include poly (butyl acrylate) (e.g., FIG. 2A) with a Tg of about 220degrees Kelvin (e.g., about −53 degrees Celsius), poly (benzyl acrylate)(e.g., FIG. 2B) with a Tg of about 277 degrees Kelvin (e.g., about 4degrees Celsius), poly (hexyl acrylate) (e.g., FIG. 2C) with a Tg ofabout 215 degrees Kelvin (e.g., about −58 degrees Celsius), poly(cyclohexyl acrylate) (e.g., FIG. 2D) with a Tg of about 288 degreesKelvin (e.g., about 15 degrees Celsius), poly (hexyl methacrylate)(e.g., FIG. 2E) with a Tg of about 268 degrees Kelvin (e.g., about −5degrees Celsius), or poly (isopropyl acrylate) (e.g., FIG. 2F) with a Tgof about 271 degrees Kelvin (e.g., about −2 degrees Celsius). In someembodiments, the grafting monomer (R_(g)) may interact with an acid, andas such the grafting monomer (R_(g)) may include a base such as amonomer having a given basicity. Thus, in some embodiments, the aciddissociation constant, pK_(a) of the grafting monomer (R_(g)) is greaterthan 7 and less than 13. In at least some embodiments, the pK_(a) of thegrafting monomer (R_(g)) is greater than 7 and less than 10. In someexamples, the grafting monomer (R_(g)) may include one or morefunctional groups such as an NH₃ group, a 1°-3° amine group, an OH⁻group, an NCS⁻ group, an alkenyl group, a phenol group, a C5-C20heterocyclic group, or a CN group. Additional examples of the graftingmonomer (R_(g)) are provided in FIGS. 3A-3C. By way of example, theetching resistance monomer (R_(e)) has a high etch resistance andincludes an aromatic compound. In some cases, the etching resistancemonomer (R_(e)) includes at least one of styrene and a phenoliccompound. Additional examples of the etching resistance monomer (R_(e))are provided in FIGS. 4A-4C.

In various embodiments, the treatment material 100 has a molecularweight (MW) that is less than about 20,000. In at least some cases, thetreatment material 100 has a MW that is less than about 10,000. In someembodiments, the unit of MW is grams per mole. Additionally, in someembodiments, the treatment material 100 may include a polymer chainincluding a block copolymer or a random copolymer. By way of example, asolvent system (e.g., used to remove the treatment material 100) mayinclude an organic solvent. In some cases, the solvent system mayinclude one or more of n-butyl acetate (nBA), 2-heptanone, and Isoamylacetate (IAA). In some embodiments, the partition coefficient (Log P) ofthe solvent system is greater than 1.82. Referring once again to FIG.1B, and in some examples, a chemical structure of the treatment material100 may include the grafting monomer (R_(g)), the etching resistancemonomer (R_(e)), and the treatment monomer (R_(t)) bonded to A₃, A₂ andA₁, respectively, where each of A₁, A₂ and A3 may be COO— or PhO—. A₁,A₂ and A3 may in turn be bonded to a chemical backbone as part ofchemicals X, Y and Z, respectively. In some embodiments, the mole ratiosof X to Y to Z are described by X+Y+Z=1.0, 0.1<X<0.9, 0.25<Y<0.5, and0<Z<1. X_(a), X_(b) and X_(c), which are also bonded to the backbone,may be hydrogen or methyl.

As noted above, the treatment material may 100 be used to treat theresist material as part of a post-treatment process or as part of anin-situ treatment process. With reference now to FIG. 5, shown thereinis a flow chart of a semiconductor manufacturing method 500,illustrating use of the treatment material 100 as part of apost-treatment process. Additional steps may also be provided before,during, and after the method 500, and some steps described can bereplaced, eliminated, or moved before or after other steps foradditional embodiments of the method. It is also noted that the method500 is exemplary, and is not intended to limit the present disclosurebeyond what is explicitly recited in the claims that follow. The method500 will be further described below in conjunction with FIGS. 6A-6C.

In various embodiments, the method 500 begins at block 502 where asubstrate 602 is provided. By way of illustration, the substrate 602 mayinclude a bulk layer 604 and one or more layers 606, 608 formed thereon.In some examples, the bulk layer 604 includes a semiconductor wafer,such as a silicon wafer. Additionally, in some embodiments, thesubstrate 602 may include various layers, including conductive orinsulating layers formed on a semiconductor substrate (e.g., on the bulklayer 604). The bulk layer 604 and/or the one or more layers 606, 608may further include various doping configurations depending on designrequirements as is known in the art. The bulk layer 604 and/or the oneor more layers 606, 608 may also include other semiconductors such asgermanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond.Alternatively, the bulk layer 604 and/or the one or more layers 606, 608may include a compound semiconductor and/or an alloy semiconductor.Further, the bulk layer 604 and/or the one or more layers 606, 608 mayoptionally include an epitaxial layer (epi-layer), may be strained forperformance enhancement, may include a silicon-on-insulator (SOI)structure, and/or have other suitable enhancement features.

In some embodiments, the substrate 602 includes a metal, a metal alloy,a metal nitride, a sulfide, a selenide, an oxide, and/or a silicide withthe formula ‘MXa’, where M is a metal and X is N, S, Se, O, or Si with‘a’ equal to about 0.4-2.5. For example, in at least some embodiments,the substrate 602 includes one or more of Ti, Al, Co, Ru, TiN, WN2, andTaN. Alternatively, in some embodiments, the substrate 602 includes Si,a metal oxide, and/or a metal nitride with the formula ‘MXb’, where M isa metal or Si, and X is N or O with ‘b’ equal to about 0.4-2.5. Forexample, in at least some embodiments, the substrate 602 includes one ormore of SiO2, silicon nitride, aluminum oxide, hafnium oxide, andlanthanum oxide.

Generally, and in some embodiments, the substrate 602 may include anunderlayer (or material layer) to be processed (e.g., to be patterned orto be implanted). In some examples, the bulk layer 604 itself is to beprocessed. In some embodiments, the underlayer may include the one ormore layers 606, 608. In some cases, the underlayer may include a hardmask layer to be patterned. In some examples, the underlayer may includean epitaxial semiconductor layer to be ion implanted. In an embodiment,the underlayer may include a hard mask layer including material(s) suchas silicon oxide, silicon nitride (SiN), silicon oxynitride, titaniumnitride, or other suitable material or composition. In some embodiments,the underlayer may include an anti-reflection coating (ARC) layer suchas a nitrogen-free anti-reflection coating (NFARC) layer includingmaterial(s) such as silicon oxide, silicon oxygen carbide, or plasmaenhanced chemical vapor deposited silicon oxide. In various embodiments,the underlayer may include a high-k dielectric layer, a gate layer, ahard mask layer, an interfacial layer, a capping layer, adiffusion/barrier layer, a dielectric layer, a conductive layer, othersuitable layers, and/or combinations thereof. While some examples ofunderlayers have been given, such examples are not meant to be limiting,and other suitable underlayers may be equally used without departingfrom the scope of the present disclosure.

The method 500 proceeds to block 504 where a photoresist layer (orsimply a resist layer) is formed over the substrate 602, or over theunderlayer disposed on the substrate 602. In various examples, theresist layer may include at least a polymer, a photoacid generator(PAG), a quencher (base), and a solvent. In some embodiments, the resistlayer includes a positive tone resist including an acid-cleavablepolymer. By way of example, the PAG may release acid after opticalexposure (e.g., UV exposure), and the released acid may then cleave theacid-cleavable polymer in a subsequent post exposure baking (PEB) step.In some examples, after the acid cleaves the acid-cleavable polymer, thepolymer (e.g., the resist) may become more hydrophilic, and the polymermay not be able to be dissolved (e.g., by a solvent or basic solution).In some embodiments, the resist layer may alternatively include anegative tone resist including at least one of an acid catalyzedcross-linkable polymer and a polymeric pinacol. By way of example, thePAG may release acid after optical exposure (e.g., UV exposure), and thereleased acid may then catalyze the cross-linking of the acid catalyzedcross-linkable polymer or the pinacol rearrangement of the polymericpinacol. In some examples, after the cross linking or the pinacolrearrangement, the polymer (e.g., the resist) may become morehydrophobic, and the polymer may not be able to be dissolved (e.g., by abasic solution). In some cases, the resist layer may further include asurfactant, a chromophore, and a cross-linker. In some embodiments, thephotoresist polymer may have a molecular weight (MW) between about 1,000to about 20,000. In various embodiments, the resist layer is sensitiveto radiation used in a lithography exposure process and has a resistanceto etching processes (or ion implantation processes). In someembodiments, the resist layer may be formed by a spin-on coatingprocess. In some examples, prior to forming the resist layer, anadhesion layer (e.g., such as an HMDS layer) is formed over thesubstrate, or over the optional underlayer disposed on the substrate. Insome embodiments, after formation of the resist layer, and prior toperforming an exposure process, a pre-bake process may be performed, forexample, to evaporate solvents and to densify the resist layer. Invarious embodiments, the resist layer is sensitive to various types ofradiation, such as DUV radiation (e.g., 248 nm radiation from a KrFlaser or 193 nm radiation from an ArF laser), EUV radiation (e.g., 13.5nm radiation), an electron beam (e-beam), or an ion beam. Generally, invarious embodiments, the resist layer may be sensitive to radiationhaving a wavelength less than about 250 nm. In some embodiments, theresist may include a tri-layer stack that includes a resist layer over abottom anti-reflective coating (BARC) layer over an organic underlayer.

The method 500 proceeds to block 506 where the resist layer ispatterned. Generally, after formation of the resist layer, a pattern isexposed onto the resist-coated substrate. For example, in variousembodiments, the resist layer may be exposed (e.g., by a lithographicimaging system) through an intervening mask. In some embodiments, theresist layer is exposed by EUV radiation (e.g., 13.5 nm). Alternatively,in some embodiments, the resist layer may be exposed by DUV radiation(e.g., from a 248 nm KrF excimer laser or a 193 nm ArF excimer laser),X-ray radiation, an e-beam, an ion beam, and/or other suitable radiationsources. In various examples, the exposure of the resist layer may beperformed in air, in a liquid (e.g., immersion lithography), or in avacuum (e.g., for EUV lithography and e-beam lithography). In someembodiments, the radiation beam is patterned with a mask, such as atransmissive mask or a reflective mask, which may include resolutionenhancement features such as phase-shifting features and/or opticalproximity correction (OPC), and which may be performed using off-axisillumination (OAI). In some other embodiments, the radiation beam isdirectly modulated with a predefined pattern, such as an IC layout,without using a mask (such as using a digital pattern generator ordirect-write mode).

In some embodiments, after exposure of the pattern onto theresist-coated substrate, a baking process may be performed. For example,in some embodiments, after exposure of the resist layer, and prior toperforming a resist development process, a post-bake process may beperformed to stabilize and harden the developed resist layer. In someexamples, as a result of the exposure process, a latent pattern isformed in the resist layer. By way of example, the latent pattern refersto the exposed pattern on the resist layer, which will subsequentlybecome a physical resist pattern, after a developing process. In variousembodiments, the latent pattern of the resist layer may includeunexposed portions and exposed portions of the resist layer. In variousembodiments, the exposed portions of the resist layer may be physicallyor chemically changed as a result of the exposure process. In someembodiments, if a positive-tone resist has been used, the exposedportions will be dissolved during a subsequent development process. Insome cases, if a negative-tone resist has been used, the exposedportions will become insoluble and a subsequent development process mayinstead dissolve the unexposed portions.

In some embodiments, after the baking process, a development process isperformed to form a patterned resist layer, as shown in FIG. 6A. Forexample, after formation of the latent image and in various embodiments,a resist development process is performed, resulting in a patternedresist layer 610 over the substrate 602. In some embodiments, the resistdevelopment process includes a wet chemical development process, asknown in the art. As discussed above, if a positive-tone resist has beenused, the exposed portions will be dissolved during the developmentprocess, and if a negative-tone resist has been used, the exposedportions will be insoluble and instead the unexposed portions will beremoved. In at least some existing processes, the patterned resist layermay include resist patterns having significant line width roughness(LWR) (e.g., presenting as rough line edges 610A of the patterned resistlayer 610) and/or poor local critical dimension uniformity (LCDU), whichmay be a result of the LWR.

The method 500 proceeds to block 508 where the treatment material isdeposited over the patterned resist layer. With reference to the exampleof FIG. 6B, and in an embodiment of block 508, the treatment material100 may be deposited over the patterned resist layer 610, therebycoating the patterned resist layer 610 and the rough line edges 610A ofthe patterned resist layer. In some embodiments, the treatment material100 may be deposited by a spin-coating process or other suitableprocess. In some embodiments, after deposition of the treatment material100 onto the patterned resist layer 610, a baking step is optionallyperformed. In various embodiments, the treatment material 100 may bondto surfaces of the patterned resist layer 610, including surfaces of therough line edges 610A of the patterned resist layer 610. In someexamples, the treatment material 100 bonds to the surfaces of thepatterned resist layer 610 by way of hydrogen bonding, ionic bonding, orcovalent bonding.

The method 500 proceeds to block 510 where an unbonded portion of thetreatment material is removed. With reference to the example of FIG. 6C,and in an embodiment of block 510, after the coating and optional bakingof the treatment material 100, an unbonded portion of the treatmentmaterial 100 is removed. For example, the unbonded portion of thetreatment material 100 may be removed using a solvent system (e.g., asolvent material) including one or one or more of n-butyl acetate (nBA),2-heptanone, and Isoamyl acetate (IAA). In some embodiments, thepartition coefficient (Log P) of the solvent material is greater than1.82. In various examples, portions of the treatment material 100 notbonded to the patterned resist material 610 are removed (e.g., portionsof the treatment material 100 not in contact with the resist material),while portions of the treatment material 100 that are bonded to thepatterned resist material 610 remain bonded to the resist materialduring the treatment material removal process. After removal of thetreatment material and as a result of the bonding of the treatmentmaterial to the patterned resist layer, the treated patterned resistlayer includes resist patterns having minimal line width roughness (LWR)and excellent local critical dimension uniformity (LCDU). Stated anotherway, the treated patterned resist layer includes patterns having a lowerLWR than the untreated patterned resist layer. Thus, the treatedpatterned resist layer also has substantially smooth line edges andsurfaces 610B, compared to the rough edges and surfaces 610A of theuntreated patterned resist layer.

In some examples, after the treatment process and formation of thetreated patterned resist layer, a fabrication process may be performedto the exposed substrate or underlayer through openings 612 of thetreated patterned resist layer, where the treated patterned resist layeris used as a mask. In some embodiments, such a fabrication process mayinclude an etching process applied to the underlayer using the treatedpatterned resist layer as an etch mask, thereby transferring the patternfrom the treated patterned resist layer to the underlayer.Alternatively, in some embodiments, the fabrication process may includean ion implantation process using the treated patterned resist layer asan ion implantation mask, thereby forming various doped features (e.g.,within the underlayer). In some embodiments, other fabrication processesmay alternatively be performed while using the treated patterned resistlayer as a mask.

With reference now to FIG. 7, shown therein is a flow chart of asemiconductor manufacturing method 700, illustrating use of thetreatment material 100 as part of an in-situ treatment process.Additional steps may also be provided before, during, and after themethod 700, and some steps described can be replaced, eliminated, ormoved before or after other steps for additional embodiments of themethod. It is also noted that the method 700 is exemplary, and is notintended to limit the present disclosure beyond what is explicitlyrecited in the claims that follow. The method 700 will be furtherdescribed below in conjunction with FIGS. 8A-8D.

In various embodiments, the method 700 begins at block 702 where asubstrate 802 is provided. By way of illustration, the substrate 802 mayinclude a bulk layer 804 and one or more layers 806, 808 formed thereon.In various embodiments, the substrate 802, including the one or morelayers 806, 808, may be substantially as described above. For example,the substrate 802 may include an underlayer (or material layer) to beprocessed (e.g., to be patterned or to be implanted). In some examples,the bulk layer 804 itself is to be processed. In some embodiments, theunderlayer may include the one or more layers 806, 808. The method 700proceeds to block 704 where a resist layer is formed over the substrate.In various embodiments, a resist layer 810 is formed over the substrate802, or over the underlayer disposed on the substrate 802, as shown inFIG. 8A. The resist layer may be substantially the same as previouslydescribed. In some embodiments, after formation of the resist layer 810,and prior to performing an exposure process, a pre-bake process may beperformed, for example, to evaporate solvents and to densify the resistlayer 810. In various embodiments, the resist layer 810 is sensitive tovarious types of radiation, as described above.

The method 700 proceeds to block 706 where a pattern is exposed onto theresist layer. Referring again to FIG. 8A, a pattern is exposed onto theresist-coated substrate through an intervening mask 812 and using aradiation source 814, substantially in a manner as described above. Insome embodiments, after exposure of the pattern onto the resist-coatedsubstrate, a baking process may be performed (e.g., post-exposure bake).For example, in some embodiments, after exposure of the resist layer,and prior to performing a resist development process, a post-bakeprocess may be performed to stabilize and harden the developed resistlayer. In some examples, as a result of the exposure process, a latentpattern is formed in the resist layer, as described above. In at leastsome existing processes, the latent pattern may include a pattern havingsignificant line width roughness (LWR) (e.g., presenting as rough lineedges 810A of the latent pattern).

The method 700 proceeds to block 708 where an in-situ treatment processof the resist layer is performed. In accordance with some embodiments,an in-situ treatment process 815 of the resist layer (e.g., using thetreatment material) is performed after the exposure and post-exposurebake processes, and before a subsequent development process. Statedanother way, an in-situ treatment process of the resist layer (e.g.,using the treatment material) is performed after formation of the latentpattern, and before a subsequent development process. In someembodiments, the treatment material disclosed herein may be depositedover the patterned resist layer, for example, by a spin-coating process,a vapor deposition process, or other suitable process. With reference toFIGS. 8B and 8C, and by the in-situ treatment process 815 of block 708,the treatment material 100 may diffuse through portions of the exposedor unexposed layers of the resist 810, thereby coating sidewalls of thelatent pattern within the resist layer (e.g., including rough line edges810A of the latent pattern). In various embodiments, the treatmentmaterial 100 may bond to surfaces of the latent pattern within theresist layer by way of hydrogen bonding, ionic bonding, or covalentbonding.

The method 700 proceeds to block 710 where a development process isperformed and an unbonded portion of the treatment material is removed.In some embodiments, after the in-situ treatment process of block 708, adevelopment process is performed to form a patterned resist layer 810B,as shown in FIG. 8D. Stated another way, after formation of the latentimage and after the in-situ treatment process, a resist developmentprocess is performed, resulting in the treated patterned resist layer810B, similar to the treated patterned resist layer described above. Insome embodiments, the resist development process is as described above.Additionally, in some embodiments, the resist development process mayremove portions of the treatment material 100 not in contact withsidewalls of the latent pattern within the resist, while portions of thetreatment material 100 that are bonded to surfaces of the latent patternwithin the resist remain bonded to the resist material after thedevelopment process. In some cases, a baking process may be performedafter the development process. Thus, after the development process, andas a result of the in-situ treatment process, the treated patternedresist layer 810B includes resist patterns having minimal line widthroughness (LWR) and excellent local critical dimension uniformity(LCDU). Stated another way, the treated patterned resist layer 810Bincludes patterns having a lower LWR than an untreated patterned resistlayer, and for example, a lower LWR than the LWR of the latent pattern.Thus, the treated patterned resist layer also has substantially smoothline edges and surfaces, compared to the rough edges and surfaces of anuntreated patterned resist layer and compared to the rough edges andsurfaces of the latent pattern. In some examples, after the in-situtreatment process and formation of the treated patterned resist layer, afabrication process may be performed to the exposed substrate orunderlayer through openings 816 of the treated patterned resist layer,as described above.

As discussed above, additional steps may also be provided before,during, and after the methods 500 and/or 700, and some steps describedcan be replaced, eliminated, or moved before or after other steps foradditional embodiments of the method. For example, in an embodiment, thesubstrate 602 or the substrate 802 includes a semiconductor substrateand the methods 500 and/or 700 proceed to forming fin field effecttransistor (FinFET) devices. In such an example, the methods 500 and/or700 may further include forming a plurality of active fins in thesemiconductor substrate. Additionally, and in furtherance of thisexample, the methods 500 and/or 700 may further include etching thesemiconductor substrate to form trenches in the semiconductor substrate;filling the trenches with a dielectric material; performing a chemicalmechanical polishing (CMP) process to form shallow trench isolation(STI) features; epitaxial growth and/or recessing of the STI features toform fin-like active regions. In some embodiments, the methods 500and/or 700 include other steps to form a plurality of gate electrodes,gate spacers, doped source/drain regions, contacts for gate/source/drainfeatures, etc. In some embodiments, subsequent processing may formvarious contacts/vias/lines and multilayers interconnect features (e.g.,metal layers and interlayer dielectrics) on the substrate, configured toconnect the various features to form a functional circuit that mayinclude one or more devices (e.g., one or more FinFET devices). Infurtherance of the example, a multilayer interconnection may includevertical interconnects, such as vias or contacts, and horizontalinterconnects, such as metal lines. The various interconnection featuresmay employ various conductive materials including copper, tungsten,and/or silicide. In one example, a damascene and/or dual damasceneprocess is used to form a copper related multilayer interconnectionstructure. Those of ordinary skill in the art having benefit of thisdisclosure will recognize other embodiments and applications of thetreatment material, without departing from the scope of the presentdisclosure.

It is also noted that the treatment material and methods of the presentdisclosure are not limited to a particular substrate type, mask type,resist type, radiation source (e.g., radiation wavelength), and/orlithography system type. For example, the treatment material and methodsthereof may be applied to resist used to pattern features and/or deviceson a variety of substrate materials such as silicon, germanium, siliconcarbide (SiC), silicon germanium (SiGe), diamond, compoundsemiconductors, alloy semiconductors, and the substrate may optionallyinclude one or more epitaxial layers (epi-layers), may be strained forperformance enhancement, may include a silicon-on-insulator (SOI)structure, and/or have other suitable enhancement features. Embodimentsof the present disclosure may further be applicable to processesemploying reflective masks (e.g., such as used for extreme ultraviolet(EUV) lithography), transmissive masks, binary intensity masks,phase-shifting masks, as well as other mask types known in the art. Insome examples, embodiments disclosed herein may be applied to processesemploying various types of resist such as poly(methyl methacrylate)(PMMA), SU-8, an EUV resist, a positive-tone resist, a negative-toneresist, or other types of resist as known in the art. Additionally,embodiments of the present disclosure are applicable to variouslithography system/aligner types such as a contact aligner, a proximityaligner, a projection aligner, or an EUV lithography system. Thus,embodiments of the present disclosure may further be applicable tosystems employing any of a variety of radiation sources (radiationwavelengths) such as UV light, deep UV (DUV) light, EUV light, or otherradiation sources as known in the art.

The various embodiments described herein offer several advantages overthe existing art. It will be understood that not all advantages havebeen necessarily discussed herein, no particular advantage is requiredfor all embodiments, and other embodiments may offer differentadvantages. For example, embodiments discussed herein include a materialcomposition and method for treating a resist material, and therebyimproving at least LWR and local critical dimension uniformity (LCDU).In various embodiments, the material composition may be used to treatthe resist material as part of an in-situ treatment process or as partof a post-treatment process. In particular, as a result of the materialcomposition and treatment methods disclosed herein, embodiments of thepresent disclosure provide for treated patterned resist layers havingsubstantially smoother line edges and surfaces compared to the rougheredges and surfaces of untreated patterned resist layers. Thus,embodiments of the present disclosure serve to overcome variousshortcomings of at least some current resist compositions and methods.

Thus, one of the embodiments of the present disclosure described amethod that includes forming a patterned resist layer on a substrate,where the patterned resist layer has a first line width roughness. Invarious embodiments, the patterned resist layer is coated with atreatment material, where a first portion of the treatment materialbonds to surfaces of the patterned resist layer. In some embodiments, asecond portion of the treatment material (e.g., not bonded to surfacesof the patterned resist layer) is removed, thereby providing a treatedpatterned resist layer, where the treated patterned resist layer has asecond line width roughness less than the first line width roughness.

In another of the embodiments, discussed is a method where a resistlayer is exposed on a substrate to form a latent pattern within theresist layer. Thereafter, an in-situ treatment process of the exposedresist layer is performed, where the in-situ treatment process depositsa treatment material within the exposed resist layer and on sidewalls ofthe latent pattern. In various examples, after performing the in-situtreatment process, the exposed resist layer is developed to provide atreated patterned resist layer.

In yet another of the embodiments, discussed is a method ofsemiconductor device fabrication including forming a resist layer over asubstrate. In some embodiments, an exposure process is performed to theresist layer, where the exposure process is performed using an EUV lightsource and projected onto the resist layer through an intervening maskincluding a circuit pattern. In various examples, after performing theexposure process, the exposed resist layer is developed to form apatterned resist layer, where the patterned resist layer includes thecircuit pattern, and where the patterned resist layer has a first linewidth roughness. Thereafter, the patterned resist layer is coated with atreatment material, where a first portion of the treatment materialbonds to surfaces of the patterned resist layer. In some embodiments, asecond portion of the treatment material is removed to provide a treatedpatterned resist layer, where the treated patterned resist layer has asecond line width roughness less than the first line width roughness.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method, comprising: exposing a resist layer ona substrate; performing an in-situ treatment process of the exposedresist layer, wherein the in-situ treatment process deposits a treatmentmaterial within the exposed resist layer, wherein a first portion of thetreatment material bonds to surfaces of a latent pattern within theexposed resist layer, wherein the treatment material includes one ormore of a first monomer, a second monomer different than the firstmonomer, and a third monomer different than both the first and secondmonomers; and developing the exposed resist layer, thereby removing asecond portion of the treatment material to provide a treated patternedresist layer.
 2. The method of claim 1, further comprising: afterexposing the resist layer and prior to performing the in-situ treatmentprocess, performing a baking process.
 3. The method of claim 1, whereinthe removing the second portion includes removing the second portionusing a solvent including at least one of n-butyl acetate (nBA),2-heptanone, and Isoamyl acetate (IAA).
 4. The method of claim 3,wherein the solvent has a partition coefficient greater than about 1.82.5. The method of claim 1, wherein the first monomer includes at leastone of an aliphatic compound, a C4-C20 alkyl group, a cycloalkyl group,a C4-C20 saturated or unsaturated hydrocarbon ring, and a C5-C20heterocyclic group.
 6. The method of claim 1, wherein the first monomerhas a glass transition temperature (Tg) below about 80 degrees Celsius.7. The method of claim 1, wherein the second monomer includes a basehaving an acid dissociation constant (pK_(a)) value greater than 7 andless than
 13. 8. The method of claim 1, wherein the second monomerincludes at least one of an NH₃ group, a 1°-3° amine group, an OH⁻group, an NCS⁻ group, an alkenyl group, a phenol group, a C5-C20heterocyclic group, and a CN group.
 9. The method of claim 1, whereinthe third monomer includes at least one of styrene and a phenoliccompound.
 10. The method of claim 1, wherein the treatment material hasa molecular weight (MW) that is less than about 20,000.
 11. A method,comprising: exposing a resist layer on a substrate to form a latentpattern within the resist layer; performing an in-situ treatment processof the exposed resist layer, wherein the in-situ treatment processdeposits a treatment material within the exposed resist layer and onsidewalls of the latent pattern, wherein the treatment material includesone or more of a first monomer, a second monomer different than thefirst monomer, and a third monomer different than both the first andsecond monomers; after performing the in-situ treatment process,developing the exposed resist layer to provide a treated patternedresist layer.
 12. The method of claim 11, wherein the latent pattern hasa first line width roughness, and wherein the treated patterned resistlayer has a second line width roughness less than the first line widthroughness.
 13. The method of claim 11, wherein depositing the treatmentmaterial within the exposed resist layer and on the sidewalls of thelatent pattern includes bonding the treatment material to surfaces ofthe latent pattern by way of hydrogen bonding, ionic bonding, orcovalent bonding.
 14. The method of claim 11, wherein depositing thetreatment material within the exposed resist layer and on the sidewallsof the latent pattern includes diffusing the treatment material throughexposed or unexposed portions of the resist layer.
 15. The method ofclaim 11, wherein the treatment material includes the first monomer, thesecond monomer different than the first monomer, and the third monomerdifferent than both the first and second monomers.
 16. A method ofsemiconductor device fabrication, comprising: forming a resist layerover a substrate; performing an exposure process to the resist layer,wherein the exposure process is performed using an EUV light source andprojected onto the resist layer through an intervening mask including acircuit pattern; after performing the exposure process, developing theexposed resist layer to form a patterned resist layer, wherein thepatterned resist layer includes the circuit pattern, and wherein thepatterned resist layer has a first line width roughness; coating thepatterned resist layer with a treatment material, wherein a firstportion of the treatment material bonds to surfaces of the patternedresist layer, wherein the treatment material includes one or more of afirst monomer, a second monomer different than the first monomer, and athird monomer different than both the first and second monomers;removing a second portion of the treatment material to provide a treatedpatterned resist layer, wherein the treated patterned resist layer has asecond line width roughness less than the first line width roughness;and prior to developing the exposed resist layer, performing an in-situtreatment process of the exposed resist layer, wherein the in-situtreatment process deposits the treatment material within the exposedresist layer and on sidewalls of a latent pattern within the resistlayer.
 17. The method of claim 16, wherein the circuit pattern includesone or more FinFET device circuit patterns.
 18. The method of claim 16,wherein the removing the second portion includes removing the secondportion using a solvent including at least one of n-butyl acetate (nBA),2-heptanone, and Isoamyl acetate (IAA).
 19. The method of claim 16,wherein the treatment material includes a first monomer and a secondmonomer that is different than the first monomer.
 20. The method ofclaim 16, wherein the treatment material includes the first monomer, thesecond monomer different than the first monomer, and the third monomerdifferent than both the first and second monomers.